In today's extremely large-scaled integrated circuits, IC designs are now the system. Almost all IC designs are SOC (system of the chip) level of complexity. In order to successfully complete these large design projects, design re-use and use of IP provided by 3rd parties is a must. hd Lab's Design Style Guide is packed with proven techniques,know-how and design rules that will lead to successful SOC projects, design re-use initiatives and IP development.
As of December 19th 2003, sale of Design Style Guide will be terminated.
We appreciate your interest and support of this product.
The Design Style Guide can be purchased in two ways:
1) Printed material
2) Corporate License
Printed Material Version
* Techniques and know-how for design re-use is presented in an easy to understand, organized manner.
* Design rules for SOC and IP developments are explained and presented.
* Jointly developed by 11 Japanese companies sponsored STARC (Semiconductor Technology Academic Research Center) truly a "de facto" standard
* Sold in a bounded book format
* 42,000 yen per copy
* Outline/Table of Contents
1. Synchronous and asynchronous design, ways to design re-set signals, multiple clocks
2. Design environment well-suited for ASIC/FPGA based design
3. HDL coding styles to improve circuit quality, design efficiency and circuit re-use
4. Simulation technique, debug methodology and fault simulation test techniques
DESIGN STYLE GUIDE 2002
Verilog-HDL version sample （DSG2002_veri_sample.pdf）
DESIGN SYYLE GUIDE 2001
Verilog-HDL version sample (DSG2001_veri_sample.pdf)
Corporate License Version
* Licensed for customer sites
* In addition to the printed material, various multimedia formats (web etc.) are provided.
* Can be further customized to reflect customers' own design rules (Optional)
* On-site training of the style guide contents are also available (Optional)
* Outline/Table of Contents
1. Synchronous and asynchronous design, ways to design re-set signals, multiple clocks
2. Design environment well suited for ASIC/FPGA based design
3. HDL coding styles to improve circuit quality, design efficiency and circuit re-use
4. Simulation technique, debug methodology and fault simulation test techniques
5. Synthesis techniques and know-how for very large-scale complex circuits
6. Project management techniques involving multiple design teams
* For further information and quotation, please contact our sales group.
STARC/HDLAB Design Style Guide Partners Program
* Following third party software supports Design Style Guide (STARC Policy).
* For further information, please refer to following web sites.
